Analog-to-digital and digital-to-analog converters have been described in the past utilizing a simple solution that is based on the periodic charging and discharging of a capacitor. These are sometimes referred to as the Shannon-Rack decoders. These types of decoders employ a constant current source that is utilized to charge a capacitor through a switch. For the digital-to-analog conversion, the output on the capacitor, after a number of switching cycles, represents the analog value. A clock is necessary to synchronize the operation of the decoder in conjunction with the binary input. A weighting factor is provided during each interval of time that the capacitor is charged and discharged to ensure that the capacitor voltage is halved each half-period through discharging. Due to practical problems such as timing and the need of high precision and low-draft components, as well as a serial digital input, such a converter has never been widely utilized.
A modern version of the concept of charge weighting used in the Shannon-Rack decoder which is tailored for monolithic integration is the concept of a charge redistribution decoder. In this decoder, intermediate results are stored dynamically with minimum losses on high-precision capacitors (e.g., MOS capacitors), and are moved from one capacitor to another by MOSFET switches. One of the more widely utilized charge redistribution converter techniques is that based on successive approximation. This technique primarily utilizes capacitors having binary weighted values with the top plate of all the capacitors connected to one input of a comparator and the bottom plate switched between various voltages. The steering of the various switches is controlled by the comparator through auxiliary logic circuitry.
The conversion process is essentially performed in three steps, a sampling step, a hold step and a conversion step. In the sampling step, the top plates of the capacitors are normally connected to ground or some suitable sample reference voltage, and the bottom plates to the input voltage. This results in a stored voltage on the bottom plate which is proportional to the input voltage. In the hold step, the top plate is electrically isolated and the bottom plates are normally connected to ground or some suitable hold reference voltage. Since the charge on the top plate is conserved, it's potential goes to the negative of the input voltage. In the conversion or "redistribution" step, each individual bit is tested by sequentially connecting the bottom plate of each of the capacitors to either a redistribution reference voltage or to ground until the voltage on the top plate reaches a predetermined voltage. This is usually the trip point of the comparator.
Charge redistribution converters have also been designed utilizing a differential configuration with a positive and a negative array of capacitors connected to the differential input of a comparator. This provides a fully differential charge redistribution A/D converter which accommodates input differential signals and provides increased supply noise rejection and noise performance. However, one disadvantage of the fully differential architecture is that the common mode input voltage can be relatively high, which voltage is impressed at both the positive and negative inputs of the comparator. The output of the comparator is sensitive only to the differential voltage. As a result, the input differential signals accommodated by the differential architecture are usually less than the supply voltage, in addition to the input common mode range also being less than the supply voltage.
Operation of the comparator at various common mode voltages can result in a variation in offset error in the analog-to-digital conversion. Normally, the offset voltage of the comparator is manifested as an offset error in the conversion. This, of course, can be compensated for by various techniques. However, if the offset error is a function of a common mode input voltage, which is normally the case with conventional comparators, this will result in an error due to the common mode input voltage. Therefore, there exists a need for a circuit which minimizes the amount of error in the conversion process and the limitations of input voltage swings due to the value of the common mode input voltage.